A block diagram illustrating a prior art all digital phase-domain PLL incorporating time to digital converter (TDC) and digitally controlled oscillator (DCO) circuits with wideband frequency modulation capability is shown in FIG. 1. The ADPLL, generally referenced 10, comprises a reference phase accumulator 12, time to digital converter (TDC) system 14, phase detector 16, loop filter 18, DCO gain normalizer 20 and digitally controlled oscillator (DCO) 22. The digitally-controlled oscillator produces a digital clock CKV in the RF frequency band. In the feedforward path, the CKV clock toggles an NMOS transistor switch of the near class-E RF power amplifier (not shown) that is followed by a matching network, and then terminated with an antenna.
In the feedback path, the CKV clock is used to retime the frequency reference or FREF clock. The FREF retiming quantization error is determined by the time-to-digital converter (TDC), which is build as an array of inverter delay elements and registers, in order to compensate the quantization error by the system. An integer part of the variable phase is determined by counting the number of rising clock transitions of the DCO oscillator clock CKV. The TDC system quantizes and measures the time differences between the FREF and DCO edges, i.e. the fractional part of the variable phase. The variable phase is subtracted from the reference phase by the phase detector. The reference phase is generated by accumulating the frequency command word (FCW). The phase error samples are then sampled and then scaled and filtered to be used as the DCO tuning word.
A block diagram highlighting the use of a phase detector to generate the phase error in the prior art ADPLL of FIG. 1 is shown in FIG. 2. The circuit, generally referenced 70, comprises a reference phase accumulator 71 and phase detector 76. The reference phase accumulator comprises an adder 72 and register 74 which are operative to accumulate the frequency command word (FCW)
Like most prior art approaches to phase locked loop design, the ADPLL described above employs a phase detector which performs phase comparison between reference phase and variable phase signals. A disadvantage of basing operation of the loop on phase detection, however, is that it makes it very difficult and nearly impossible for the PLL to minimize perturbations to the loop. Perturbations to the loop may be caused, for example, by large phase errors that are generated for any number of reasons, e.g., large settling time on DCO varactor banks, frequency band switching, spikes in the output of the power amplifiers, etc. As a result, large perturbations may violate the RF system specifications or even exceed the dynamic limits of the loop and cause the phase detector to output inaccurate phase errors which are propagated through the loop filter to the DCO resulting in jumps in output frequency. It is desirable to have the PLL avoid any negative effects of these perturbations by ‘sleeping’ through them. The operation of the loop during these perturbations, however, cannot be stopped as the loop is dependent on phase and phase is the integral of frequency in time and thus cannot be stopped since accumulation of the phase must be maintained. Thus, there is potential for the loop to become unstable if the perturbation is severe enough.
There is thus a need for a mechanism that is capable of detecting a potentially disturbing perturbation at the input to the PLL. It is also desirable that in response to the detection of a perturbation, the mechanism have the capability of temporarily freezing the operation of the PLL until the perturbation has passed (at least sufficiently enough to minimize any negative impact to the loop operation).